(1) Field of the Invention
The invention relates to a framework for inter-element channel transmission and a method for the same, and more particularly to a channel transmission model and a respective methodology design, which are suitable to be operated independently and whose channel arrangement can be arbitrarily adjusted according to practical requirements.
(2) Description of the Prior Art
In a conventional framework of a computer system, various buses might be used to form a communication net among elements in the computer system. As shown in FIG. 1, a plurality of conventional buses are used to bridge a first element 10 and a second element 20, in which the first or the second elements 10 or 20 can be embodied as a CPU, a memory, a peripheral, or any the like. Generally, the bus can be classified into three categories as follows. They are:
1. A control bus for generating specific signals to control the system, mainly used to establish the communication between a CPU and a peripheral or between a CPU and a memory;
2. An address bus for determining the target address, a memory or an I/O device, of a specific signal; and
3. A data bus for single-direction or bi-direction data transmission, capable of data-reading and/or data-writing with respect to a CPU, a peripheral, or a memory.
By providing the control bus, signal flows in the computer can be predetermined. By providing the address bus, the signal can be led to the target device. Also, by providing the data bus, the read-out or the write-in data can be transmitted. However, these conventional buses have the following disadvantages.
1. Uniqueness: while a transmission job occupies a specific bus, all other jobs need to wait in queue orderly until the bus is released from the previous job. That is, the conventional bus can""t send and receive data at the same time.
2. Most data lines used for data/address buses in a computer system are 64-bit-width data lines. However, it is expectable in the near future that a bus with 128-bit-width data lines will be the mainstream. Such an increase in the bit width implies the inevitable increase in the number of pin counts for the data line as well as the bus, and will result in the difficulty of package and in the increase of size. In particular, the system controller is mostly effected by the increase of the pin count, due to its connection to most important elements.
3. In a condition of simultaneous switching (from 0 to 1, or from 1 to 0 at the same time) at parallel data/address lines, higher consumed power is inevitable and thus larger noise will effect the transmission.
Accordingly, it is an object of the present invention to provide a framework and a corresponding method for inter-element channel transmission, in which various channels are used as the communication means between elements and so that data in the system can be reasonably allocated in accordance with practical requirements. In the present invention, each channel includes a plurality of signal lines for transmitting control, data and address signals according to a predetermined communication protocol.
In a preferred embodiment of the present invention, one of the signal lines in the channel can be used to transmit clock or start flag signals. According to the present invention, the clock signal can be an inconsistent square wave for determining the data formats transmitted in the data lines by judging the duty cycle in each wave cycle. By providing a duty cycle detector to detect the duty cycle, the implicit meaning of the signals transmitted in the respective signal lines can then be realized; that is, signal lines for transmitting address signals, data signals or control signals can thus be clearly defined.
Accordingly, in another preferred embodiment of the present invention, an A/C line (address/control line) of the channel can be used to define the start and the end of transmission and to transmit the address and the control signals. The rest signal lines in the same channel are then left as the data lines for transmitting data signals. By judging the variation of signals transmitted in the A/C line, latch sequences in the data lines can then be realized. On the other hand, by judging the variation in the data lines, bit difference of the address signals transmitted in the A/C line can be also read. In the present invention, by providing a data line switch detector and an edge and starting signature detector, characteristics of signals transmitted in the data lines and the A/C line can then be detected.
Upon aforesaid arrangement of the transmission model and the methodology, each channel of the present invention can operate as a complete bus, characterized in independent operation and unique-directional transmission for both address and data signals. Also, the channels in the present invention can be properly adjusted to meet practical requirements. Thereby, mobility of signal transmission among various elements can be achieved; so that the idle transmission time for each element can be greatly reduced and, consequently, optimal transmission efficiency can be obtained. By providing the channel framework of the present invention, much benefit can be obtained in constructing a complete hardware work.